Riley Gusa

    UART, Universal Asynchronous Receiver-Transmitter, is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable. It takes bytes of data and transmits the individual bits sequentially. The data frame looks as follows:
 

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The start bit signals the receiver that a new character is coming. The next 8 bits represent the character in binary. The stop bit is the final bit that signals the receiver that the character is complete. 

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All operations of the UART hardware are controlled by an internal clock signal which runs at a multiple of the data rate, usually 16 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. To receive the data packet the receiver loops through and samples each bit and the resulting level is inputted into a shift register. After the required number of bit periods for the character length has elapsed, the contents of the shift register are made available to the receiving system. The receiver will set a flag indicating new data is available and will generate a processor interrupt to process the data.

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I implemented this in SystemVerilog on a NEXYS FGPA. The user inputted data through the keyboard, which got sent from TeraTerm to the FPGA through an FTDI into the GPIO ports. The FPGA receives the data using a custom UART receiver and outputs that data, using a custom UART transmitter, to an LCD screen. I set it up to only send one byte through the buffer, so the output on the screen is a single character. To do this I also created a baud rate generator, so the user can define what baud rate they want to send their data at. 

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